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| ADE-203-260A (Z) HM514260C/CL Series HM51S4260C/CL Series 262,144-word x 16-bit Dynamic Random Access Memory Rev. 1.0 Jun. 12, 1995 The Hitachi HM51(S)4260C/CL are CMOS dynamic RAM organized as 262,144-word x 16bit. HM51(S)4260C/CL have realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C/CL offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM51(S)4260C/CL to be packaged in standard 400-mil 40-pin plastic SOJ, standard 475-mil 40-pin plastic Zip and standard 400-mil 44-pin plastic TSOP II. Internal refresh timer enables HM51S4260C/CL self refresh operation. Features * Single 5 V (10%) * High speed -- Access time: 60 ns/70 ns/80 ns (max) * Low power dissipation -- Active mode: 825 mW/770 mW/688 mW (max) -- Standby mode 11 mW (max) 1.1 mW (max) (L-version) * Fast page mode capability * 512 refresh cycles: 8 ms 128 ms (L-version) * 2CAS byte control * 2 variations of refresh -- RAS-only refresh -- CAS-before-RAS refresh * Battery back up operation (L-version) * Self refresh operation (HM51S4260C/CL) HM514260C/CL, HM51S4260C/CL Series Ordering Information Type No. HM514260CJ-6 HM514260CJ-7 HM514260CJ-8 HM514260CZ-6 HM514260CZ-7 HM514260CZ-8 HM514260CTT-6 HM514260CTT-7 HM514260CTT-8 HM514260CLJ-6 HM514260CLJ-7 HM514260CLJ-8 HM514260CLZ-6 HM514260CLZ-7 HM514260CLZ-8 HM514260CLTT-6 HM514260CLTT-7 HM514260CLTT-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns Package 400-mil 40-pin plastic SOJ (CP-40DA) 475-mil 40-pin plastic ZIP (ZP-40) 400-mil 44-pin plastic TSOP II (TTP-44/40DB) 400-mil 40-pin plastic SOJ (CP-40DA) 475-mil 40-pin plastic ZIP (ZP-40) 400-mil 44-pin plastic TSOP II (TTP-44/40DB) Type No. HM51S4260CJ-6 HM51S4260CJ-7 HM51S4260CJ-8 HM51S4260CTT-6 HM51S4260CTT-7 HM51S4260CTT-8 HM51S4260CLJ-6 HM51S4260CLJ-7 HM51S4260CLJ-8 HM51S4260CLTT-6 HM51S4260CLTT-7 HM51S4260CLTT-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns Package 400-mil 40-pin plastic SOJ (CP-40DA) 400-mil 44-pin plastic TSOP II (TTP-44/40DB) 400-mil 40-pin plastic SOJ (CP-40DA) 400-mil 44-pin plastic TSOP II (TTP-44/40DB) 2 HM514260C/CL, HM51S4260C/CL Series Pin Arrangement HM514260CJ/CLJ Series HM51S4260CJ/CLJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS HM514260CZ/CLZSeries I/O9 2 I/O11 4 I/O12 6 I/O14 8 VSS 10 I/O0 12 I/O2 14 VCC 16 I/O5 18 I/O7 20 22 NC RAS 24 26 A0 28 A2 VCC 30 32 A4 34 A6 36 A8 UCAS 38 40 NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 I/O8 I/O10 VSS I/O13 I/O15 VCC I/O1 I/O3 I/O4 I/O6 NC WE NC A1 A3 VSS A5 A7 OE LCAS (Top View) (Bottom View) HM514260CTT/CLTT Series HM51S4260CTT/CLTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 Pin Description Pin name A0 to A8 Function Address input - - - I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS Row address A0 to A8 Column address A0 to A8 Refresh address A0 to A8 Data-in/data-out Row address strobe Column address strobe Read/write enable Output enable Power (+5 V) Ground NC NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS (Top View) 3 HM514260C/CL, HM51S4260C/CL Series Block Diagram I/O Bus & Column Decoder I/O Bus & Column Decoder I/O Bus & Column Decoder I/O Bus & Column Decoder Selector 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat Row Decoder Row Row Decoder Decoder Row Decoder Row Decoder Row Row Decoder Decoder Row Decoder Selector Selector Selector I/O4 I/O4 Buffer I/O5 Buffer I/O6 Buffer I/O7 Buffer 256 k Memory Array Mat I/O11 Buffer Peripheral Circuit I/O3 I/O3 Buffer I/O2 I/O2 Buffer I/O1 I/O1 Buffer I/O0 I/O0 Buffer I/O15 I/O15 Buffer I/O14 I/O14 Buffer I/O13 I/O13 Buffer I/O12 I/O12 Buffer I/O11 I/O5 I/O10 I/O10 Buffer I/O9 Buffer I/O8 Buffer I/O9 I/O6 I/O7 I/O8 Peripheral Circuit WE RAS Address A0,A1,A2,A3 Address A4,A5 A6,A7,A8 LCAS UCAS OE Selector Row Decoder Selector Row Decoder Selector Row Decoder Selector Row Decoder Row Row Decoder Decoder Row Row Decoder Decoder I/O Bus & Column Decoder I/O Bus & Column Decoder I/O Bus & Column Decoder I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat 4 256 k Memory Array Mat Peripheral Circuit HM514260C/CL, HM51S4260C/CL Series Operation Mode The HM51(S)4260C/CL series has the following 11 operation modes. 1. 2. 3. 4. 5. 6. Read cycle Early write cycle Delayed write cycle Read- modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle 7. 8. 9. 10. 11. Self refresh cycle (HM51S4260C/CL) Fast page mode read cycle Fast page mode early write cycle Fast page mode delayed write cycle Fast page mode read- modify-write cycle Inputs RAS H H L L L L L H to L LCAS H L L L L L H H L L L L L L L H to L H to L H to L H to L L UCAS H L L L L L H L H L H to L H to L H to L H to L L H L*2 L*2 H to L H L D H L to H H Valid Open Undefined Valid Open Fast page mode read cycle Fast page mode early write cycle Fast page mode delayed write cycle Fast page mode read-modify-write cycle Read cycle (Output disabled) WE D H H L*2 L*2 H to L D D OE D L L D H L to H D D Output Open Valid Valid Open Undefined Valid Open Open Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Self refresh cycle (HM51S4260C/CL) Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. tWCS 0 ns Early write cycle tWCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected. 5 HM514260C/CL, HM51S4260C/CL Series Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: VIH VIL Min 0 4.5 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.5 6.5 0.8 Unit V V V V Note 2 1, 2 1 1 1. All voltage referred to VSS. 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 6 HM514260C/CL, HM51S4260C/CL Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM514260C/CL, HM51S4260C/CL -6 Parameter Operating current*1, *2 Symbol ICC1 ICC2 -7 -8 RAS, LCAS or UCAS cycling tRC = min TTL interface RAS, LCAS, UCAS = VIH Dout = High-Z CMOS interface RAS, LCAS, UCAS, OE, WE VCC - 0.2 V Dout = High-Z CMOS interface RAS, LCAS, OE, WE UCAS VCC - 0.2 V Dout = High-Z tRC = min RAS = VIH, LCAS, UCAS = VIL Dout = enable tRC = min tPC = min Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 250 s tRAS 1 s, LCAS, UCAS = VIL WE, OE= VIH CMOS interface RAS, LCAS, UCAS < 0.2 V, Dout = High-Z CMOS interface RAS, LCAS, UCAS < 0.2 V, Dout = High-Z 0 V < Vin < 6.5 V 0 V < Vout < 6.5 V Dout = disable High Iout = -5.0 mA Low Iout = 4.2 mA Min Max Min Max Min Max Unit Test conditions -- -- 150 -- 2 -- 140 -- 2 -- 125 mA 2 mA Standby current -- 1 -- 1 -- 1 mA Standby current (L-version) ICC2 -- 200 -- 200 -- 200 A RAS-only refresh current*2 ICC3 Standby current*1 ICC5 -- -- 140 -- 5 -- 130 -- 5 -- 110 mA 5 mA CAS-before-RAS refresh current*2 Fast page mode current*1, *3 ICC6 ICC7 -- -- -- 140 -- 150 -- 300 -- 130 -- 130 -- 300 -- 110 mA 120 mA 300 A Battery back up current*4 ICC10 (Standby with CBR refresh) (L-version) Self-refresh mode current (HM51S4260C) Self-refresh mode current (HM51S4260CL) Input leakage current Output leakage current Output high voltage Output low voltage ICC11 -- 1 -- 1 -- 1 mA -- 200 -- 200 -- 200 A ILI ILO VOH VOL -10 10 -10 10 2.4 0 -10 10 -10 10 -10 10 -10 10 A A VCC 2.4 0.4 0 VCC 2.4 0.4 0 VCC V 0.4 V 7 HM514260C/CL, HM51S4260C/CL Series Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while LCAS and UCAS = VIH. 4. VIH > VCC - 0.2 V, 0 < VIL < 0.2 V, Address can be changed once or less while RAS = VIL 5. All the VCC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage. Capacitance (Ta = +25C, VCC = 5 V 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 10 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. LCAS and UCAS = VIH to disable Dout. 8 HM514260C/CL, HM51S4260C/CL Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *14, *15, *17, *18 Test Conditions * Input rise and fall times: 5 ns * Input timing reference levels: 0.8 V, 2.4 V * Input levels: 0 V, 3 V * Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM514260C/CL, HM51S4260C/CL -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol Min Max tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT tREF tREF 110 -- 40 60 15 0 10 0 15 20 15 15 60 10 15 0 0 3 -- -- -- -7 Min Max 130 -- 50 -- 10000 10000 -- -- -- -- 50 35 -- -- -- -- -- -- 50 8 128 -8 Min Max 150 -- 60 80 20 0 10 0 15 20 15 20 80 15 20 0 0 3 -- -- -- 10000 10000 -- -- -- -- 60 40 -- -- -- -- -- -- 50 8 128 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7 20 19 19 8 9 23 Notes 10000 70 10000 20 -- -- -- -- 45 30 -- -- -- -- -- -- 50 8 128 0 10 0 15 20 15 20 70 15 20 0 0 3 -- -- 9 HM514260C/CL, HM51S4260C/CL Series Read Cycle HM514260C/CL, HM51S4260C/CL -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol Min tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tOFF1 tOFF2 tCDD -- -- -- -- 0 0 0 30 0 0 15 Max 60 15 30 15 -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 0 35 0 0 15 Max 70 20 35 20 -- -- -- -- 15 15 -- -8 Min -- -- -- -- 0 0 0 40 0 0 15 Max 80 20 40 20 -- -- -- -- 15 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns 6 6 Notes 2, 3 3, 4, 13 3, 5, 13 23 19 16, 20 16 Write Cycle HM514260C/CL, HM51S4260C/CL -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time CAS to OE delay time Symbol Min tWCS tWCH tWP tRWL tCWL tDS tDH tCOD 0 15 10 15 15 0 15 -- Max -- -- -- -- -- -- -- 0 -7 Min 0 15 10 20 20 0 15 -- Max -- -- -- -- -- -- -- 0 -8 Min 0 15 10 20 20 0 15 -- Max -- -- -- -- -- -- -- 0 Unit ns ns ns ns ns ns ns ns 21 11 11 23 Notes 10, 19 19 10 HM514260C/CL, HM51S4260C/CL Series Read-Modify-Write Cycle HM514260C/CL, HM51S4260C/CL -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min tRWC tRWD tCWD tAWD tOEH 150 80 35 50 15 Max -- -- -- -- -- -7 Min 180 95 45 60 20 Max -- -- -- -- -- -8 Min 200 105 45 65 20 Max -- -- -- -- -- Unit ns ns ns ns ns 10 10 10, 13 Notes Refresh Cycle HM514260C/CL, HM51S4260C/CL -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol tCSR tCHR tRPC tCPN Min 10 10 10 10 Max -- -- -- -- -7 Min 10 10 10 10 Max -- -- -- -- -8 Min 10 10 10 10 Max -- -- -- -- Unit ns ns ns ns Notes 19 20 19 22 Fast Page Mode Cycle HM514260C/CL, HM51S4260C/CL -6 Parameter Fast page mode cycle time Fast page mode CAS precharge time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol Min Max tPC tCP tRASC tACP tRHCP 40 10 -- -- 35 55 80 -- -- -7 Min Max 45 10 -- -- -8 Min Max 50 10 -- -- Unit Notes ns ns 22 12 3, 13, 20 100000 -- 35 -- -- -- -- 40 65 95 100000 -- 40 -- -- -- -- 45 70 100000 ns 45 -- -- ns ns ns ns Fast page mode read-modify-write tCPW cycle CAS precharge to WE delay time Fast page mode read-modify-write cycle time tPCM 100 -- 11 HM514260C/CL, HM51S4260C/CL Series Self-refresh Mode HM51S4260C/CL -6 Parameter RAS pulse width (self-refresh) RAS precharge time (self-refresh) CAS hold time (self-refresh) Symbol tRASS tRPS tCHS Min 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit s ns ns 21 Notes 24, 25, 26 Notes: 1. AC measurements assume tT = 5 ns. 2 Assumes that tRCD < tRCD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD > tRCD (max) and tRAD < tRAD (max). 5. Assumes that tRCD < tRCD (max) and tRAD > tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 10. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS > tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD > tRWD (min), tCWD > tCWD (min), tAWD > tAWD (min) and tCPW > tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either tRCH or tRRH must be satisfied for a read cycle. 17. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 18. All the VCC and VSS pins shall be supplied with the same voltages. 19. tASC, tCAH, tRCS, tRCH, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS. 20. tCRP, tCHR, tACP, tRCH and tCPW are determined by the later rising edge of UCAS or LCAS. 21. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS. 12 HM514260C/CL, HM51S4260C/CL Series 22. tCPN and tCP are determined by the time that both UCAS and LCAS are high. 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 24. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1. 2. Each of the UCAS/LCAS should satisfy the timing specifications individually. Different operation mode for upper/lower byte is not allowed; such as following. RAS Delayed write UCAS Early write LCAS WE 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, fast page mode can be performed. RAS UCAS LCAS t UL 13 HM514260C/CL, HM51S4260C/CL Series Timing Waveforms*27 Read Cycle t RC t RAS RAS tT t RCD t CSH t RSH t CAS t RP t CRP UCAS LCAS t ASR t RAD t RAH t ASC t RAL t CAH Address Row Column t RCS t RCH WE t CAC t AA High-Z Dout t RAC t DZC Din High-Z t OAC t RRH t OFF1 Dout t OFF2 t CDD t ODD t DZO OE A @ A @ Notes: 27. 14 H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) Invalid Dout HM514260C/CL, HM51S4260C/CL Series Early Write Cycle t RC t RAS RAS tT t RCD t CSH UCAS LCAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP t RP Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z * OE : H or L 15 HM514260C/CL, HM51S4260C/CL Series Delayed Write Cycle t RC t RAS t RP RAS t CSH tT t RCD UCAS LCAS t ASR t RAH t ASC t CAH Column t CWL t RWL t RSH t CAS t CRP Address Row t RCS t WP WE t DH t DS Din Din t DZC t OEH t DZO t ODD Dout High-Z *Invalid Dout t OFF2 t COD OE * Do not enable Dout during delayed write cycle. 16 HM514260C/CL, HM51S4260C/CL Series Read-Modify-Write Cycle t RWC tT t RP RAS t CRP t RCD UCAS LCAS t ASR t RAH t RAD t ASC t CAH Address Row t RCS Column t CWL t CWD t AWD t WP t RWL WE t RWD t AA t CAC t RAC t DZC Din High-Z t DS t DH Din Dout High-Z t OAC Dout t OFF2 t DZO t ODD t OEH OE 17 HM514260C/CL, HM51S4260C/CL Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP UCAS LCAS t RAH t ASR Address Row t RPC t CRP Dout High-Z * OE, WE : H or L ** Refresh address : A0 - A8 (AX0 - AX8) 18 HM514260C/CL, HM51S4260C/CL Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS ** t RP t RC t RAS ** t RP RAS tT t RPC t CPN UCAS LCAS t RPC t CSR t CHR t CPN t CSR t CHR t CRP Address t OFF1 Dout High-Z * WE : H or L > ** Do not extend tRAS _ tRAS (max). Untested self refresh mode may be activated and loss of data may be resulted (HM514260C/CL). 19 HM514260C/CL, HM51S4260C/CL Series Fast Page Mode Read Cycle t RASC t RHCP RAS tT t CSH t RCD UCAS LCAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t RAL t CAH t CAS t CP t PC t CAS t CP t RSH t RP t CRP t CAS Address Row Column t RCS t RCS t RCH Column t RCS t RCH Column t RRH t RCH WE t CDD t DZC High-Z t ODD t CAC t AA t RAC t OFF1 Dout High-Z t DZO t OAC t DZO t OFF2 OE Dout t AA t ACP t OFF1 t DZC t CDD High-Z t CAC High-Z t CAC t AA t ACP t DZO Dout t ODD t OFF2 t OAC t OFF2 t OFF1 t ODD t DZC t CDD Din Dout t OAC 20 HM514260C/CL, HM51S4260C/CL Series Fast Page Mode Early Write Cycle t RASC t RP RAS t CSH tT t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP UCAS LCAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column t WCS t WCH Column t WCS t WCH t WCS Column t WCH WE t DS t DS t DH t DH t DS t DH Din Din Din Din Dout High-Z * OE : H or L 21 HM514260C/CL, HM51S4260C/CL Series Fast Page Mode Delayed Write Cycle t RASC t RP RAS t CSH tT t RCD UCAS LCAS t ASR t RAH t ASC t CAH t ASC t CAH t CWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t ASC t CAH Address Row Column Column Column t CWL t RCS t WP t WP t CWL t WP t RWL WE t DH t DS t RCS t DS t DH t RCS t DS t DH Din Din Din Din t OEH Dout t ODD High-Z OE 22 HM514260C/CL, HM51S4260C/CL Series Fast Page Mode Read-Modify-Write Cycle t RASC RAS t RCD tT t CP t PCM t CP t RP t CRP UCAS LCAS t ASR t RAD t RAH t CAH t ASC t ASC t ACP t CAH t CAH tASC Address Row Column t AWD t CWD t RWD t CWL t WP Column t AWD t RCS t CWD t CPW t CWL t WP Column t CPW t AWD t RCS t CWD t CWL t RWL t WP t RCS WE t DS t DZC t CAC t DH t DZC t CAC t DS t DH t ACP tDZC High-Z t CAC t OEH t OAC Dout t OFF2 t OEH t DS t DH Din High-Z t AA t RAC t OAC Din t DZO t OEH High-Z t AA t OAC Dout t OFF2 Din Din Dout High-Z Dout t DZO t OFF2 t DZO OE t ODD t ODD t ODD 23 HM514260C/CL, HM51S4260C/CL Series Self Refresh Cycle t RP t RASS t RPS RAS tT t RPC t CPN UCAS LCAS t CRP t CSR t CHS Address t OFF1 Dout High-Z 24 * WE OE : H or L The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1.Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of tRP. 2.If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 4.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. HM514260C/CL, HM51S4260C/CL Series Package Dimensions HM514260CJ/CLJ Series HM51S4260CJ/CLJ Series (CP-40DA) 25.80 26.16 Max 40 21 10.16 0.13 11.18 0.13 Unit: mm 1 0.74 1.265 Max 20 3.50 0.26 2.85 0.12 0.63 Min 0.43 0.10 1.27 0.10 9.40 0.25 HM514260CZ/CLZ Series (ZP-40) Unit: mm 50.82 51.84 Max 2.8 Min 12.07 Max 10.42 1 0.50 + 0.08 - 0.12 0.25 - 0.05 + 0.10 40 1.27 M 2.85 0.3 1.045 Max 2.54 25 HM514260C/CL, HM51S4260C/CL Series Package Dimensions HM514260CTT/CLTT Series HM51S4260CTT/CLTT Series (TTP-44/40DB) Unit: mm 44 18.41 18.81 Max 35 32 23 1 10 13 0.80 0.21 M 1.005 Max 22 0.27 0.07 10.16 11.76 0.2 0 - 5 1.20 Max 0.08 Min 0.18 Max +0.075 -0.025 0.10 0.145 0.50 0.10 26 0.68 HM514260C/CL, HM51S4260C/CL Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor product. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales office when planning to use the products in MEDICAL APPLICATIONS. 6. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel : Tokyo (03) 3270-2111 Fax : (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA 94005-1835 U. S. A. Tel : 415-589-8300 Fax : 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher StraBe 3 D-85622 Feldkirchen Munchen Tel : 089-9 91 80-0 Fax : 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Wihtebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel : 0628-585000 Fax : 0628-778322 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Habour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel : 27359218 Fax : 27306071 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel : 535-2100 Fax : 535-1533 27 HM514260C/CL, HM51S4260C/CL Series Revision Record Rev. 0.0 1.0 Date May. 31, 1994 Jun. 12, 1995 Contents of Modification Initial issue Drawn by S. Hatano Approved by A. Endo Change format Change of package type: TTP-40DB to TTP-44/40DB Recommended DC operating condition Deletion of VIL (others) AC Characteristics Addition of input levels to test conditions: 0 V, 3 V tRSH min:20/20/20 ns to 15/20/20 ns tRWL min:20/20/20 ns to 15/20/20 ns tCWL min:20/20/20 ns to 15/20/20 ns Deletion of notes 24 Change of Timing waveforms Read-modify-write cycle, Fast page mode read cycle Fast page mode read-modify-write cycle CAS-before-RAS refresh cycle Self refresh cycle 28 |
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